Current mode drivers are commonly used in a variety of automatic test and measurement applications to generate fast and precise waveforms for stimulating a device under test (DUT). Owing to the relatively low impedance at a transmission line input, and the ease with which currents can be rapidly turned on and off, such drivers are useful for applications requiring very fast edge transitions and rapid toggle rates. For example, differential signalling standards common in technologies such as Low Voltage Differential Signalling (LVDS), IEEE-1394 Firewire, Universal Serial Bus (USB), etc. . . . are well suited to current mode drive techniques.
FIG. 1 schematically illustrates a conventional current-mode drive approach (hereinafter “driver 10”). Specifically, FIG. 1 shows a differential switching element (shown as a bipolar emitter coupled pair comprising QA and QB) used to rapidly switch a programmable current generated by a current source IO. The current is imposed at a summing node S formed by the transmission line and a backmatching impedance, RB. Although not necessary, it may be useful to include a cascode transistor QC to improve various performance aspects of the circuit. For the purpose of this discussion, it may be assumed that any current applied to the emitter of transistor QC is passed unchanged to its collector.
In this example, the impedance of the transmission line generally has a 50 ohm characteristic impedance, and the matching impedance resistor RB is selected to match the transmission line as closely as possible. As the switched current is drawn from the summing node S, a voltage waveform is generated and transmitted down the transmission line, where it eventually reaches the DUT (or terminating impedance ZO, which terminates the end of the line to a terminating potential, VTERM). The magnitude of the change in voltage waveform at the summing node S is given by the magnitude of the current source, IO, multiplied by the parallel combination of the transmission line impedance and the backmatching resistor RB. Accordingly, by varying the magnitude of the current source, it is possible to generate a variety of output waveform amplitudes.
To provide a high level reference potential, it is common practice to connect the back terminal of the transmission line matching resistor, RB, to a low impedance node via an appropriate static buffer (or dynamic driver as the case may be). When the current IO (i.e., generated by a current source that also is identified herein as IO) is switched away from the summing node S, the voltage present at the input to the transmission line is simply that of the buffer driving RB. FIG. 1 identifies this voltage as VH. It also is common practice to receive another voltage, VL, and to calculate the magnitude of IO so that, when necessary, the current IO is sufficient to pull the voltage at the summing node S down from VH to VL. Although convenient for many applications, this calculation need not be implemented by specific circuitry included with the current mode driver 10. Instead, it can be calculated explicitly by the user or by some other apparatus. If the differential switching action of the emitter coupled pair is complete (i.e., there is no leakage in the off state), then the voltage at the terminated end of the transmission line, accounting for all impedances and reference levels, is given by Equation 1 below:
                              V          OUT                =                                                            R                B                            ⁢                              V                TERM                                      +                                          Z                o                            ⁢                              V                H                                      -                                          R                B                            ⁢                              Z                o                            ⁢              Iout                                                          R              B                        +                          Z              o                                                          (                  Equation          ⁢                                          ⁢          1                )            where each term is as defined in the discussion above and IOUT is that part of IO that passes though QB and QC after accounting for any alpha losses that may be contributed by those two nonideal devices.
The dynamic operation of the current mode driver 10 shown in FIG. 1 can be understood with reference to FIGS. 2A and 2B. The emitter coupled pair is driven by a signal applied to the base of each of the transistors QA and QB. The base drive signal can be single ended as depicted in FIG. 2A, or it can be differential as depicted in FIG. 2B. Both methods may be equally applied to the discussion that follows.
When the voltage VA is less than the voltage VB, the transistor QA turns off and the transistor QB turns on. As a result, the current IO is shunted toward the summing node S by QB and the voltage on the summing node S drops to the low state. Conversely, when VA is again made greater than VB, transistor QA turns on and QB turns off. The current IO is then shunted away from the summing node S by QA and the voltage waveform rises back to the high state. This cycle is repeated in accordance with the waveform pattern desired at the DUT.
Undesirably, when the dynamic operation is carried out at high speed, several parasitic charge storage elements intrinsic to switching devices QA and QB can cause the effective current IO to depart from the desired simple on-off nature discussed above. Consequently, because the voltage waveform at the summing node S is directly proportional to this current, undesirable aberrations and asymmetries in the current are superimposed on the generated waveform.
FIG. 3 schematically shows parasitic capacitors, CP, across each of the base-emitter junctions of QA and QB. These capacitors represent the intrinsic junction capacitances associated with each of the transistors, as well as the minority charge storage that occurs in the base region of the devices. In general, the capacitors typically are not equal because the intrinsic junction component is a function of bias voltage across the base-emitter junctions, and the charge storage component is a function of the current flowing through each device. As the differential pair switches current from one side to the other, these conditions change substantially during circuit operation.
As the base drive voltages are varied, transient currents are injected through the dynamic parasitic capacitances where they eventually find their way into the collector of transistor QB, and, consequently, into the summing node S. Significant aberrations are thus imposed onto the desired voltage waveform simply by the switching action of the differential pair.
FIG. 4 illustrates such a representative waveform received by the DUT. As shown, the falling edge transition of the waveform is much faster than the rising edge, and that the falling edge also exhibits a significant overshoot. These undesirable attributes are a direct consequence of the parasitic current injected through the parasitic capacitors during the switching transient. To achieve adequate performance in high speed applications, however, it is important to minimize these aberrations.